module particular(in_particular,out_particular,rd_temp,rd_particular);

input rd_temp;
input [7:0] in_particular;
output [9:0] out_particular;
output rd_particular;

wire rd_temp;
wire [7:0] in_particular;
reg [9:0] out_particular;
reg rd_particular;
reg [10:0]out_temp;

always@(in_particular)begin
	case(in_particular)
		8'b00011100:		out_temp <= 11'b00011110100;		//K28.0
		8'b00111100:		out_temp <= 11'b10011111001;		//k28.1
		8'b01011100:		out_temp <= 11'b10011110101;		//k28.2
		8'b01111100:		out_temp <= 11'b10011110011;		//k28.3
		8'b10011100:		out_temp <= 11'b00011110010;		//k28.4
		8'b10111100:		out_temp <= 11'b10011111010;		//k28.5
		8'b11011100:		out_temp <= 11'b10011110110;		//k28.6
		8'b11111100:		out_temp <= 11'b00011111000;		//k28.7
		8'b11110111:		out_temp <= 11'b01110101000;		//K23.7
		8'b11111011:		out_temp <= 11'b01101101000;		//K27.7
		8'b11111101:		out_temp <= 11'b01011101000;		//K29.7
		8'b11111110:		out_temp <= 11'b00111101000;		//K30.7
		default:				out_temp <= 11'b00111110100;
	endcase
end

always@(rd_temp or out_temp)begin
if(rd_temp)
	out_particular <= ~out_temp[9:0];
else
	out_particular <= out_temp[9:0];

end

always@(rd_temp or out_temp)begin
if(out_temp[10])
	rd_particular <= ~rd_temp;
else
	rd_particular <= rd_temp;

end




endmodule